1. Field of the Invention
The present invention relates generally to integrated circuits (IC) and more specifically to a method and apparatus for high-speed integer multiplication of signed and/or unsigned operands.
2. Related Art
An integer multiplier unit generally receives two integers (operands) to be multiplied and provides their product as an output. Often, each integer is received as an N-bit number and the result is provided as a (2*N) bit number. Integer multiplier units are often contained in arithmetic logic units (ALU) that perform various arithmetic operations on digital representations of numbers.
A multiplier unit may have to handle both signed and unsigned numbers. In the case of unsigned numbers, all the bits together generally represent the magnitude. In the case of signed numbers, the digits can represent either a positive number or a negative number. Signed numbers are represented using conventions such as twos complement representations.
In addition, a multiplier unit may need to indicate whether the result of the multiplication cannot be represented by the output bits (called an overflow condition). For example, in multiplication of two signed numbers represented in 2's complement form of N-bits each, a overflow would occur when both the signed numbers are maximum negative numbers (i.e., 1 in the most significant bit and 0 in all other positions), assuming (2N−1) bits of output.
The multipliers units may need to be implemented meeting several requirements. For example, it may be desirable to implement units while meeting requirements such as higher throughput performance and/or lower area consumed, etc.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.